1. Technical Field
The present invention is directed to processes for device fabrication, and, more particularly, photodetector devices, in which two crystalline substrates with different crystal lattices are bound together.
2. Art Background
Processes for fabricating certain semiconductor devices require that two wafers, each having a crystal lattice that is different from the other, be bound together. For example crystalline III-V substrates (e.g. Indium Gallium Arsenide substrates (InGaAs)) are bound to crystalline silicon substrates to fabricate p-i-n photodetectors. Such devices are described in Hawkins, A., et al., "Silicon heterointerface photodetector," Appl. Phys. Lett., Vol. 68:26, pp. 3692-3694 (1996) (Hawkins et al. hereinafter). As used herein, III-V substrates are semiconductor compounds in which one of the elements is from column III of the Mendeleef Periodic Table and one of the elements is from column V of that Table.
Hawkins et al. describe a process for fabricating avalanche photodetector devices in which a silicon wafer is fused directly to an InGaAs surface of an indium phosphide (InP) substrate. In the Hawkins et al. process, an InGaAs surface is grown on the InP substrate by metalorganic chemical vapor deposition (MOCVD). The bonding surface of the silicon wafer is an epitaxial silicon layer grown on an n.sup.+ substrate with a shallow p-type implant at the surface. After bonding, the InP substrate is subsequently removed leaving only the InGaAs layer bound to the silicon substrate. The bonding is performed by pressing the surfaces of the two substrates together for 20 minutes at 650.degree. C. in an H.sub.2 atmosphere.
The epitaxial layers of the resulting device 10 are illustrated in FIG. 1. Starting from the topmost epitaxial layer, there is a p.sup.+ -doped InGaAs layer 20, which is used for ohmic contact. Underlying layer 20 is the intrinsic InGaAs layer 25 which is used for photon absorption. Layer 25 is fused to layer 30, which was a n-type silicon implanted with boron. Layer 30 functions as a multiplication region for the detector.
After the above described structure is formed, the epitaxial layers 20 and 25 are etched to form isolated devices. To isolate the devices, a patterned metal layer 60 of Au/Zn is formed over layer 20 and the portions of layers 20 and 25 are not covered by the mask are etched away. Layer 60 is a top p-type contact. After etching, a dielectric layer 70 is formed on the sidewalls of the remaining portions of layers 20 and 25. An n-type metal contact layer 80 is formed on the exposed portion 85 of the silicon substrate 30.
Hawkins et al. states that the device described therein shows potential for high speed, high gain operation, etc. However, the quality of the devices depends on, among other things, the quality of the silicon-InGaAs interface. Accordingly, a process for forming a high quality interface between the two different surfaces is desired.